module SRAM(clk,
			rstn,
	    	addr,
	   		write,
	    	byte_strb,
	    	wdata,
	    	rdata,
	    	rvalid);

//parameter declarations
parameter DATA_WIDTH   = 32;
parameter MEMORY_WIDTH = 1024;
parameter ADDR_WIDTH   = 10; //log2(MEMORY_WIDTH);
parameter STRB_WIDTH   = 4; //log2(DATA_WIDTH);

//signals declarations
input	 						clk;
input 							rstn;
input 		[ADDR_WIDTH-1:0] 	addr;
input 							write;
input 		[STRB_WIDTH-1:0]	byte_strb;
input 		[DATA_WIDTH-1:0] 	wdata;
output 	reg [DATA_WIDTH-1:0] 	rdata;
output 	reg 					rvalid;

reg [DATA_WIDTH-1:0] mem [2**ADDR_WIDTH-1:0];
  reg [DATA_WIDTH-1:0] memreg;
integer i;

//  assign rdata = (rstn == 0)? 0/*: (write != 0)? 0rdata*/ : mem[addr];

  always @(posedge clk or negedge rstn) begin
	if (rstn == 0) begin
		for(i = 0; i < MEMORY_WIDTH; i = i + 1'b1)
			mem[i] <= {DATA_WIDTH{1'b0}};
	rvalid <= 1'b0;
	end
	else if (addr < 10'd231 && write == 1) begin
      //$display($time," addr=%b",addr);
	  for(i = 0; i<STRB_WIDTH; i = i + 1'b1)
            if(byte_strb[i]) begin
		mem[addr][8*i+:8] <= wdata[8*i+:8];
				rvalid <= 1'b1;
            	memreg[8*i+:8] = wdata[8*i+:8];
            	//$display($time," data is written at strb[%1d]::%h\n",i,memor);
            end
	end
    
	else if(addr >10'd230) begin
		rvalid <= 1'b0;
	end
end
  
  	always @(negedge write) begin
      if(addr < 10'd231 && write == 0) begin
          rdata = mem[addr];
        memreg <= rdata;
          rvalid <= 1'b1;   //indicates that the read transfer has valid data
      end
    end
  always @(write) begin
    if(addr <10'd231)
      rvalid  = 1'b1;
    else if(addr > 10'd230)
      rvalid = 1'b0;
  end
/*
function integer log2;
	input integer value;
	begin
		value = value-1;
		for(log2 = 0; value>0; log2=log2+1)
			value = value>>1;
	end
endfunction */
endmodule
